In FIG. 1A and FIG. 1B an emitter switched thyristor (EST) 100 is shown, which comprises a wafer 10 having an emitter and a collector side 22, 27, on which sides an emitter electrode 2 and a collector electrode 25 are arranged. On the emitter side 22, a planar or trench gate electrode 7 is arranged, which comprises an electrically conductive gate layer 72, a further gate layer 76 and an insulating layer 74, which insulates the gate layer 72 and 76 from any layer of the first or second conductivity type in the wafer 10 and from each other. FIG. 1A shows a top view on the device 100, whereas FIG. 1B shows a cut along the line A-A in FIG. 1A.
Like in an IGBT, on the emitter side 22, an n doped first emitter layer 3, which extends to a region below the gate layer 72 and a p doped base layer 4 surrounding the first emitter layer 3 are arranged. The first emitter layer 3 and the base layer 4 contact the emitter electrode 2 at an emitter contact area 21. The device further comprises on the emitter side 22 a second n doped emitter layer 35, which is insulated from the emitter electrode 2 by the insulating layer 74. The second emitter layer 35 extends from a region below the gate layer 72 to a region below a further gate layer 76, which completely surrounds the gate layer 72.
Towards the collector electrode 25, a lowly (n−) doped drift layer 5 and a p doped collector layer 6 are arranged.
In this device, a MOS channel 140 is formable from the first emitter layer 3 via the base layer 4 to the second emitter layer 35. In the device, another channel in form of a thyristor channel 120 is formable during operation from the second emitter layer 35 via the base layer 4 to the drift layer 5.
The EST uses a cascade concept, in which a low voltage MOSFET is integrated in series with a thyristor structure, such that by turning off the MOSFET, the thyristor is turned off. Due to the shorted base layer the EST provides a MOS voltage controlled turn-on switching, a higher diode safe operating area and handling fault conditions when compared to the IGCT. Such a device has limited short circuit capability depending on its low voltage MOSFET blocking and higher on-state snapback effects.
Also the on-state losses are higher due to the low voltage MOSFET channel resistance than for a prior art IGCT. The base layer is shorted in the EST devices, so that the thyristor structure enhancement effect is reduced due to hole drainage, and hence this results in higher on-state losses. The on-state suffers from a snap-back effect before the thyristor areas are latched since conduction occurs initially through the two channels.
U.S. Pat. No. 6,091,987 describes a dual EST device, in which a first and second emitter region as well as a first and second base region are separated by the drift layer. Due to the distance between the two emitter regions and the presence of both base regions in between, there is no MOS channel formable in this device. The thyristor channels are not connected to the IGBT cell. Such a device results in high on-state losses due to a strong contribution of the IGBT drainage.